instruction execution

英 [ɪnˈstrʌkʃn ˌeksɪˈkjuːʃn]

美 [ɪnˈstrʌkʃn ˌeksɪˈkjuːʃn]

网络  指令执行

计算机

英英释义

noun

• (computer science) the process of carrying out an instruction by a computer
  Synonym:execution

双语例句

• Pipeline is dealing with instruction, including instruction decode, issue, and execution.
  流水线正在处理指令，包括指令解码、发布和执行。
• A technique whereby the receiver fetches the next instruction before completing execution of the previous instruction, in order to increase processing speed.
  在前一条指令全部执行完之前就开始取下一条指令，以提高处理速度的一种技术。
• In the traditional Cache, the Cache hit ratio is insured only by the address locality of memory reference instruction stream during program execution, it restricts the improvement of Cache hit ratio.
  在传统的Cache中，仅仅依靠程序执行时访存指令流地址的局域性来保证较高的Cache命中率，使得Cache命中率的提高受到限制。
• In other words, software interrupts always occur at the beginning of an instruction execution cycle.
  换句话说，软件中断常常在指令运行周期的开始。
• Composite electronic System is the hinge of the Pico-satellite, which undertakes the work of data processing, data storage, data transmission, Instruction code transmission and Instruction execution.
  综合电子系统是皮卫星的数据和指令枢纽，承担皮卫星数据处理、数据存储、数据传输及指令收发、响应等重要任务，是皮卫星的核心组成部分。
• Characteristics of the microprocessor are fast speed and nimble instructions. The way of raising speed is to adopt pipelining in instruction execution.
  它的运算速度提高的途径是指令的执行采用流水线方式，指令缓冲部件IB采用两个体交替接收指令和执行指令的办法来减少取指令的等待时间。
• Bochs was developed purely in the C++ language for interpreted x86 instruction execution and platform emulation.
  对于解译的x86指令执行和平台仿真，Bochs完全是用C++语言开发的。
• In the instruction execution pipeline stage, scalable pipeline technology was adopted to realize the video processing instruction.
  为有效实现扩展指令，处理器执行级采用了可扩展流水级技术。
• As the core of SOC, CPU ′ s performance is mostly determined by instruction ′ s execution efficiency. Pipeline increases the instruction ′ s execution pace and improves the CPU ′ s performance.
  作为SOC的核心，CPU的性能主要取决于指令的执行效率，而采用流水线方式大大增加了指令的执行速度，提高了CPU的性能。
• This paper has discussed the relationship between the machine cycle and instruction execution time for superscalar RISC architecture, issuing multiple instructions in one machine cycle. Several new design features of superscalar RISC architecture with single execution unit and multiple function units have been analysed.
  本文讨论超标量RISC结构中单周期发多条指令中周期和执行指令时间的相对关系，并分析了新型超标量RISC结构的实现方案，其中包括具有单个执行部件和多个执行部件的结构。